Low-Power and Compact Successive Approximation ADC for Bio-Electronic Chips

For both the electrical stimulation and recording of cultured neurons, the CMOS-based microelectrode arrays (MEAs) are one of the most promising electronic devices used nowadays. To ensure a robust transmission of the information between the chip and external devices, the MEA chip requires integrated analog-to-digital converters (ADCs). Moreover, the presence of a large number of read-out channels on chip poses stringent requirements on both area and power consumption for the design of the ADCs. Thus, this Master’s thesis work proposes a low-power and compact successive approximation register (SAR) ADC for such bio-electronic chips. In this thesis, some low-power ADC topologies are first investigated and the SAR ADC is finally chosen, that is the optimum solution for the application. The choice of multiplexing the read-out channels of the MEA chip for the analog-to-digital conversion is then presented while the requirements for the ADC are derived. In this work, the design of each part of the converter is described, starting from the switched-capacitor array which is usually used as a sample and hold (S/H) as well as a digital-to-analog converter (DAC). The size of the switches that are providing the signals to the DAC is optimized considering the timing requirements. Furthermore, low power solutions are proposed for the comparator while good performances are achieved for both noise and speed. A successive approximation register logic is finally used to provide the digital control signals. The performance of the SAR ADC is evaluated with post-layout simulations. All the preliminary requirements are met and the proposed converter represents a promising solution for low-power applications. In conclusion, the specifications of the entire data-conversion system are compared with the ADCs currently implemented on the MEA device and a possible improvement of the chip is presented.